chiselWare is a batteries-included open-source ecosystem for Verilog IP cores written in Chisel, a Scala-based hardware construction language. Its goal is to make open-source digital IP trustworthy enough for real designs by pairing freely available cores with a consistent standard for how they are written, verified, and documented.
Every chiselWare core follows the chiselWare Standard, which covers coding conventions, simulation and formal verification, synthesis across multiple configurations, licensing, and provenance. Cores that meet the standard are certified through an automated design review. A companion Developer’s Guide and a containerized development kit give contributors a complete, ready-to-use toolchain.
Most chiselWare cores are released under the Apache 2.0 license.
The project grew out of a talk by Rocksavage at the 61st Design Automation Conference in 2024. Since then it has been developed and tested through university capstone projects, in which student teams have built production-quality cores and platform components using the chiselWare methodology.
chiselWare is under active development and has not yet reached its 1.0 release. If you are interested in becoming an early developer of chiselWare cores, please send an email to info@chiselware.org and we will get back you on how to go about that in the pre-1.0 era.
